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Building on the field proven capability of Teledyne DALSA’s Xcelera frame grabber series, the Xtium™-CL MX4 is based on industry standard PCI Express™ PCIe 2.0 expansion bus to deliver high speed access to host memory. The new Xtium series of camera link frame grabbers offers higher bandwidth to sustain Camera Link® 80-Bit modes over longer cable distances and supports a wide variety of area and line scan color/monochrome cameras, all in a compact, half-length, single slot solution.
The Xtium-CL MX4 takes full advantage of PCIe PCIe 2.0 x4 platform to deliver a bandwidth in excess of 1.7GB/s, while at the same time supporting PCIe Gen 1.0 slot to deliver 850MB/s. The newly engineered, on-board, Data Transfer Engine (DTE) produces maximum bandwidth without the need for specialized motherboards or chipsets. By enabling maximum sustained throughput and ready-to-use image data, the Xtium-CL MX4 minimizes CPU usage and improves processing times for the host applications. In addition, the Xtium series has been engineered with enhanced memory architecture allowing it to handle different sensor tap topologies while sustaining color decoding at the maximum frame/line rate.
The Xtium-CL MX4 offers built-in, robust electrical signals for external event synchronization, and status notification LEDs. One or more boards can be synchronized to acquire images from multiple area or line scan cameras simultaneously. The Xtium-CL MX4 supports one Base, Medium, Full or 80-bit mode with Base/Medium/Full PoCL capabilities, as well as 2 independent base camera link cameras.
The Xtium series is engineered to meet the ever-increasing image resolution and faster frame rates of today’s camera technology. So in addition to PCIe PCIe 2.0 x4 and Camera Link, upcoming models will support Camera Link HS as well as other emerging interface standards on a PCIe PCIe 2.0 x8 platform.
Teledyne DALSA's Sapera LT SDK is a free image acquisition and control toolkit for Teledyne DALSA 2D/3D, GigE, Camera Link, Camera Link HS cameras, and frame grabbers.
| Part Number | OR-Y4C0-XMX00 |
| Board Type | PCIe |
| Host Bus | PCI Express Gen3 x8 |
| Board Interface | Camera Link |
| Connectors | Data: 2 x SDR (mini Camera Link) Camera Contro & GPIOs: 1 x DH60-27pin on main bracket 1 x 26-pin for internal connections Multi-board sync: 1 x 16 shrouded connector |
| Camera Format | 2x CameraLink Base or 1x CameraLink Medium, Full or 80-bit (Deca) |
| Transmission Rate | 85 MHz |
| Pixel Format | 8, 10, 12, 14 and 16-bit/pixel |
| Number of Camera Taps | 1 Tap – 8/10/12/14/16-bit mono/bayer; 8/10/12-bit RGB 2 Taps – 8/10/12-bit mono/bayer; 8-bit RGB 3 Taps – 8/10/12-bit mono/bayer 4 Taps – 8/10/12-bit mono/bayer64-bits: 8 Taps – 8-bit mono/bayer Full packed 8-bit RGB/BGR/RGBY 80-bit: 8-Taps – 10-bit/pixel mono/bayer 10 Taps – 8-bit/pixel mono/bayer Packed 8/12-bit RGB/BGR or Packed 8-bit Bi-Color |
| Camera Control | External Trigger input, Strobe output, Quadrature Encoder Input |
| GPIO | 4 Opto-coupled inputs, usable as trigger inputs 8 LvTTL outputs, usable as strobe outputs |
| Frame Buffer | 512 MB |
| Features | Power Over Camera Link (PoCL), Input Lookup Tables, Flat-field/Flat-line Correction, Bayer decoding, Bi-color conversion Dead Pixel (3 x 2) replacement, User programmable 3 x 3 convolution filter, Metadata, Strobe cycling/line-by-line |
| Software | Sapera LT SDK, Sapera Vision Software |
| OS Support | Windows 7 (32-bit)*, Windows 7 (64-bit)*, Windows 8 (32-bit), Windows 8 (64-bit), Windows 10 (32-bit), Windows 10 (64-bit), Linux (64-bit), WoW64 |
*Contact us for more details.
Datasheet