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The Teledyne Dalsa Xtium2™-CL MX4 high performance camera link frame grabber features an industry standard PCI Express™ (PCIe) Gen 3.0 expansion bus with a sustained bandwidth of more than 1.7Gb/s that delivers high speed access to the host memory. It's fully compatible with PCIe 2.x, and is Camera Link Rev 2.1 standard compliant.
The Xtium2-CL MX4 offers built-in, robust electrical signals for external event synchronization, and status notification LEDs. One or more boards can be synchronized to capture images from multiple area or line scan cameras simultaneously. The Xtium2-CL MX4 supports one Base, Medium, Full or 80-bit mode with Base/Medium/Full PoCL capabilities, as well as 2 independent base camera link cameras.
The Xtium2-CL MX4 has the same feature set as Xtium-CL MX4 and some additional enhancements. Read these documents if you are using Xtium-CL MX4 frame grabbers and want to move to the new Xtium2-CL MX4 frame grabber, or want use the Xtium2-CL MX4 and Xtium-CL MX4 frame grabbers interchangeably, Converting Xtium-CL-MX4 to Xtium2-CLMX4 frame grabbers, and Using Xtium2 CL MX4 and Xtium CL MX4 interchangeably.
Teledyne DALSA's Sapera LT SDK is a free image acquisition and control toolkit for Teledyne DALSA 2D/3D, GigE, Camera Link, Camera Link HS cameras, and frame grabbers.
| Part Number | OR-Y4C0-XMX00 |
| Bandwidth | Input Camera Link camera: up to 850 MB/s in frame grabber memory PCIe bus output: up to 1.5 GB/sec sustained (PCIe payload @ 512 bytes) |
| Board Type | PCIe |
| Host Bus | PCI Express Gen3 x8 |
| Board Interface | Camera Link |
| Connectors | Data: 2 x SDR (mini Camera Link) Camera Contro & GPIOs: 1 x DH60-27pin on main bracket 1 x 26-pin for internal connections Multi-board sync: 1 x 16 shrouded connector |
| Camera Format | 2x CameraLink Base or 1x CameraLink Medium, Full or 80-bit (Deca) |
| Transmission Rate | 85 MHz |
| Pixel Format |
Mono: 8, 10, or 12-bit/pixel RGB: 8, 10 or 12-bit/pixel/color Bayer: 8, 10 and 12-bit/pixel Bicolor (RG,BG): 8-bit/color (line scan) |
| Number of Camera Taps | 1 Tap – 8/10/12/14/16-bit mono/bayer; 8/10/12-bit RGB 2 Taps – 8/10/12-bit mono/bayer; 8-bit RGB 3 Taps – 8/10/12-bit mono/bayer 4 Taps – 8/10/12-bit mono/bayer64-bits: 8 Taps – 8-bit mono/bayer Full packed 8-bit RGB/BGR/RGBY 80-bit: 8-Taps – 10-bit/pixel mono/bayer 10 Taps – 8-bit/pixel mono/bayer Packed 8/12-bit RGB/BGR or Packed 8-bit Bi-Color |
| Camera Control | External trigger input, strobe output, quadrature encoder input |
| GPIO | 4 Opto-coupled inputs, usable as trigger inputs 9 LvTTL outputs, usable as strobe outputs |
| Frame Buffer | 1024 MB on-board memory (shared with processing functions) |
| Features | Power Over Camera Link (PoCL), input lookup tables, flat-field/flat-line correction, bayer decoding, bi-color conversion dead pixel (3 x 2) replacement, user programmable 3 x 3 convolution filter, metadata, strobe cycling/line-by-line |
| Software | Sapera LT SDK |
| OS Support | Windows 11 (64-bit), Windows 10 (64-bit), Windows 10 (32-bit) through WOW64, Linux (64-bit) |
| Input Camera Port | Up to 2 cameras |
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Datasheet